Buffer page roll implementation for PCI-X block read transactions

ABSTRACT

A computer system containing logic for processing a read block transaction from a PCI-X device. A technique is also disclosed for processing a read block transaction from a PCI-X device. The technique is defined by PCI-X specifications wherein the read block transaction is processed accordingly in a computer system. The technique determines whether the transaction is a read block and whether the transaction crosses a memory boundary. The technique also determines whether a page roll is required and administers one if it is required. Furthermore, the technique provides a means for reading and delivering the data to a PCI-X device.

FIELD OF THE INVENTION

The present invention relates generally to PCI-X systems and, moreparticularly, to management of read transactions in PCI-X controlledsystems. Even more particularly, the present invention provides amechanism to process data transactions using a buffer page roll.

BACKGROUND OF THE RELATED ART

This section is intended to introduce the reader to various aspects ofart, which may be related to various aspects of the present invention,which are described and/or claimed below. This discussion is believed tobe helpful in providing the reader with background information tofacilitate a better understanding of the various aspects of the presentinvention. Accordingly, it should be understood that these statementsare to be read in this light, and not as admissions of prior art.

A conventional computer system typically includes one or more centralprocessing units (CPUs) and one or more memory subsystems. Computersystems also include peripheral devices for inputting and outputtingdata. Some common peripheral devices include, for example, monitors,keyboards, printers, modems, hard disk drives, floppy disk drives, andnetwork controllers.

One of the important factors in the performance of a computer system isthe speed at which the CPU operates. Generally, the faster the CPUoperates, the faster the computer system can complete a designated task.One method of increasing the speed of a computer is using multiple CPUs,commonly known as multiprocessing. However, the addition of a faster CPUor additional CPUs can result in different increases in performanceamong different computer systems. Although it is the CPU that executesthe algorithms required for performing a designated task, in many casesit is the peripherals that are responsible for providing data to the CPUand storing or outputting the processed data from the CPU. When a CPUattempts to read or write to a peripheral, the CPU often “sets aside”the algorithm that is currently executing and diverts to executing theread/write transaction (also referred to as an input/output transactionor an I/O transaction) for the peripheral. As can be appreciated bythose skilled in the art, the length of time that the CPU is diverted istypically dependent on the efficiency of the I/O transaction.

Although a faster CPU may accelerate the execution of an algorithm, aslow or inefficient I/O transaction process associated therewith cancreate a bottleneck in the overall performance of the computer system.As the CPU becomes faster, the amount of time executing algorithmsbecomes less of a limiting factor compared to the time expended inperforming an I/O transaction. Accordingly, the improvement in theperformance of the computer system that could theoretically result fromthe use of a faster CPU or the addition of additional CPUs may becomesubstantially curtailed by the bottleneck created by the I/Otransactions. Moreover, it can be readily appreciated that anyperformance degradation due to such I/O bottlenecks in a single computersystem may have a stifling affect on the overall performance of acomputer network in which the computer system is disposed.

As CPUs have increased in speed, the logic controlling I/O transactionshas evolved to accommodate these transactions. Thus, most I/Otransactions within a computer system are now largely controlled byapplication specific integrated circuits (ASIC). These ASICs containspecific logic to perform defined functions. For example, PeripheralComponent Interconnect (PCI) logic is instilled within buses andbridges, which govern I/O transactions between peripheral devices andthe CPU. Today, PCI logic has evolved into the Peripheral ComponentInterconnect Extended (PCI-X) to form the architectural backbone of thecomputer system. PCI-X logic has features that improve upon theefficiency of communication between peripheral devices and the CPU. Forinstance, PCI-X technology increases bus capacity to more than eighttimes the conventional PCI bus bandwidth. For example, a 133 MB/s systemwith a 32 bit PCI bus running at 33 MHz is increased to a 1066 MB/ssystem with the 64 bit PCI bus running at 133 MHz.

An important feature of the new PCI-X logic is that it can providebackward compatibility with PCI enabled devices at both the adapter andsystem levels. Backward compatibility allows PCI controlled devices tooperate with PCI-X logic. Although the devices will, operate at theslower PCI speed and according to PCI specifications, the devices may becompatible to the new logic governing PCI-X transactions. Furthermore,PCI-X devices will run according to PCI-X specifications, while PCIdevices will operate according to PCI specifications without having anadverse affect on the PCI-X devices.

PCI-X logic allows a requesting device to make only one data request andrelinquish the bus, rather than holding the bus to poll for a response.PCI-X logic also enables the requesting device to specify in advance thespecific number of bytes requested, thus eliminating the inefficiency ofprefetches. Additionally, PCI-X bus logic incorporates an attributephase, split transaction support, optimized wait states, and standardblock size movement.

PCI-X logic provides an attribute phase that uses a 36-bit attributefield which describes bus transactions in more detail than theconventional PCI bus logic. This field includes information about thesize of the transaction, the ordering of transactions, and the identityof the transaction initiator. Furthermore, the attribute field in thePCI-X standard incorporates the transaction byte count, which allows thebridge to determine exactly how much data to fetch from the memory. Theattribute phase feature of PCI-X logic also incorporates relaxedordering, sequence number, transaction byte count, andnon-cache-coherent transactions.

As PCI-X logic is incorporated into the next generation of buses, itbecomes important to handle transaction requests efficiently. Generally,peripheral devices initiating read block transactions target the PCI-Xbridge. As a transaction is initiated, a buffer is allocated within thebridge. The bridge stores the information about the transaction, such asits starting address, length and so on. In the PCI-X specification,split transactions require the bridge logic to generate a replytransaction with the requested data. Thus, the PCI-X bridge stores thetransaction in a queue and replies to the transaction according topriority. Normally, a buffer holding a read block transaction isrestricted to containing data within a certain memory boundary, andthese queues have limitations on the address boundaries a transactioncan cross. Particularly, if the data string crosses a memory boundarythen the transaction will not be completed properly. Instead, it will bedelivered to the requester incomplete. Although PCI-X specificationallows read transactions to cross any address boundary, only the datathat does not cross the memory boundary will be delivered to therequester.

The present invention may address one or more of the problems discussedabove.

SUMMARY OF THE INVENTION

Certain aspects commensurate in scope with the originally claimedinvention are set forth below. It should be understood that theseaspects are presented merely to provide the reader with a brief summaryof certain forms the invention might take and that these aspects are notintended to limit the scope of the invention. Indeed, the invention mayencompass a variety of aspects that may not be set forth below.

In accordance with one aspect of the present invention, there isprovided a computer system that provides ordering of a sequence ofevents to complete a transaction. When a data transaction is initiatedto a computer system, a series of events occurs to efficiently reply tothe transaction. At the time a transaction is made, the system logicinquires whether the transaction is governed by PCI-X specifications.Specifically, the PCI-X transaction inquiry generally occurs at thebridge or bus level. As a transaction is initiated, a buffer isallocated for the storage of data. If the transaction is governed byPCI-X specifications rather than the conventional PCI specifications,the system determines whether the transaction is a read blocktransaction. Next, the data requested is separated into a part before amemory boundary and a second part after the memory boundary. The datawithin the first part of the memory boundary is read and returned to therequester. Once the data within the first part of the memory boundary isreturned to the requester, the system initiates a page roll., wherebythe data which crosses the memory boundary is read and returned to therequester.

The invention monitors the data flow, delivers the data within thememory boundary to the initiator, and retains the data, which crossesthe memory boundary. As the data is returned to the requester, theinvention replaces the starting address of the separated data stringwith the memory boundary address. The invention also replaces the numberof bytes requested, with the number of bytes beyond the memory boundary.The system reads the remaining data requested and delivers it to therequester. This completes the PCI-X transaction.

In accordance with another aspect of the present invention, there isprovided a computer system that provides ordering of a sequence ofevents for a specific transaction using a plurality of buffers.Specifically, the system allocates a plurality of buffers for a singlePCI-X transaction that crosses a memory boundary. As a transaction isinitiated, two buffers are allocated to a single read block transaction.Moreover, in this particular embodiment, a page roll is not required,but instead the data is read using the two buffers. The data requestedis stored within a plurality of buffers, and returned to the requester,according to the PCI-X ordering rules.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages of the invention will become apparentupon reading the following detailed description and upon reference tothe drawings in which:

FIG. 1 illustrates a diagram of an exemplary computer system inaccordance with the present invention;

FIG. 2 illustrates a flow chart of one embodiment of a technique forprocessing a PCI-X read transaction involving a page roll detectionmethod;

FIG. 3 illustrates a flow chart of one embodiment of an operationdescribed in FIG. 2 for the page roll detection method;

FIG. 4 illustrates a flow chart depicting logic for a page rollgeneration;

FIG. 5 illustrates a flow chart depicting an algorithm for calculatingthe total number of cachelines;

FIG. 6 illustrates a flow chart depicting an algorithm for calculatingthe number of cachelines required before a memory boundary;

FIG. 7 illustrates a flow chart of an alternative embodiment depicting atechnique for processing a PCI-X read transaction involving the use oftwo buffers;

FIG. 8 illustrates a flow chart depicting synchronization logic when twobuffers are allocated to a single transaction in the embodiment of FIG.7; and

FIG. 9 illustrates a flow chart depicting synchronization logic afterallocation of two buffers to a single transaction in the embodiment ofFIG. 7.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments of the present invention will bedescribed below. In an effort to provide a concise description of theseembodiments, not all features of an actual implementation are describedin the specification. It should be appreciated that in the developmentof any such actual implementation, as in any engineering or designproject, numerous implementation-specific decisions must be made toachieve the developers' specific goals, such as compliance withsystem-related and business-related constraints, which may vary from oneimplementation to another. Moreover, it should be appreciated that sucha development effort might be complex and time consuming, but wouldnevertheless be a routine undertaking of design, fabrication, andmanufacture for those of ordinary skill having the benefit of thisdisclosure.

Turning now to the drawings, and referring initially to FIG. 1, amultiprocessor computer system, for example a Proliant 8500 PCI-X fromCompaq Computer Corporation, is illustrated and designated by thereference numeral 10. In this embodiment of the system 10, multipleprocessors 12 control many of the functions of the system 10. Theprocessors 12 may be, for example, Pentium, Pentium Pro, Pentium II Xeon(Slot-2), or Pentium III Xeon processors available from IntelCorporation. However, it should be understood that the number and typeof processors are not critical to the technique described herein and aremerely being provided by way of example.

Typically, processors 12 are coupled to a processor bus 14. Asinstructions are sent and received by the processors 12, the processorbus 14 transmits data between the individual processors 12 and a switch16. The switch 16 directs signals between the processor bus 14, cacheaccelerator 18, and a memory controller 20. Although a crossbar switchis shown in this embodiment, any suitable type of switch may be used inthe operation of the system 10. Generally, the switch 16 couples to theprocessor bus 14, cache accelerator 18, and the memory controller 20.When instructions are sent from an input source, the switch 16 directsthe instructions towards either the processor bus 14, cache accelerator18, or the memory controller 20.

The memory controller 20 is coupled to the switch 16 and the memory 22.When data needs to be retrieved from the memory 22, the instructions aresent via the memory controller 20 to request information from the memory22. The memory controller 20 may be of any type suitable for such asystem 10. It should be understood that the number and type of memory,switches, memory controllers, and cache accelerators are not critical tothe technique described herein, and are merely being provided by way ofexample.

The memory 22 in the system 10 is generally divided into groups of bytescalled cachelines. Bytes in a cacheline may comprise several variablevalues. Cachelines in the memory 22 are moved to the cache for use bythe processors 12 whenever the processors 12 need one of the valuesstored in that particular cacheline. Each location within the memory 22is permanently labeled with a unique address. Access to a particularlocation is then obtained by specifying the address of the data.

The switch is also coupled to an Input/Output (I/O) bus 24. The I/O bus24 is coupled to PCI-X bridges 26A-D. Further, each PCI-X bridge 26A-Dis coupled to multiple PCI-X buses 28A-D. Finally, each PCI-X bus 28A-Dterminates at a series of slots or I/O interfaces 30A-D. The PCI-Xbridges 26A-D contain logic that govern many input/output transactionsor requests. Generally, each of the PCI-X bridges 26A-D is anapplication specific integrated circuit (ASIC). The PCI-X bridges 26A-Dmay include address and data buffers, as well as arbitration and busmaster control logic for the PCI-X buses 28A-D. The PCI-X bridges 26A-Dmay also include miscellaneous system logic. These miscellaneous logicaldevices may include counters and timers, an interrupt controller forboth the PCI-X buses 28A-D and I/O bus 24, and power management logic.

Generally, a transaction is initiated by a requester, i.e., a peripheraldevices coupled to one of the I/O interfaces 30A-D. For example, anoperator may initiate a transaction using, for instance, tape drives,CD-ROM drives, or other peripheral storage devices. If the transactionis conducted through a peripheral device (not shown) that does not havePCI-X capabilities, the PCI-X buses 28A-D and the PCI-X bridges 26A-Dare capable of administering the transaction using PCI specifications.As a transaction is initiated by a peripheral device, the I/O interface30A-D checks whether PCI-X or PCI specifications are used to manage thetransaction. The transaction is then ordered within the PCI-X bus 26A-Dand transmitted to the PCI-X bridge 26A-D. The scope of the transactionis reviewed, and the necessary data is obtained from the memory 22 andreturned to the requester.

FIG. 2 illustrates a flowchart, which represents PCI-X logic for pageroll detection. In this particular embodiment, bridges 26A-D contain thelogic depicted in FIG. 2, however the logic may be located at anysuitable place within the system 10. Generally, at the time a read blocktransaction is allocated a buffer, the logic within the PCI-X bridge26A-D inquires whether the read block transaction is governed by a PCI-Xtransaction thereby granting a PCI-X allocation (block 32). If thebridge 26A-D does not detect a PCI-X transaction, then the bridge 26A-Dperforms a cyclical function to check for a new PCI-X transaction. Oncethe bridge 26A-D allocates a buffer to the transaction, the bridge 26A-Dlogic then inquires into whether the transaction is a memory read blocktransaction that crosses a memory boundary (block 34). It should benoted that a buffer is allocated once a new transaction is registeredwithin the bridge 26A-D. In the present embodiment, the memory boundarylevel is set every 4 KB, however, the boundary address may be set at anylevel suitable to the system 10.

If the bridge 26A-D detects a memory read block transaction and thetransaction crosses a 4 KB memory boundary, then a page roll attributeis set to a logical one (block 36). However, if the bridge 26A-D doesnot detect a memory read block transaction, or if the 4 KB memoryboundary is not crossed by the requested data, then the page rollattribute is set to a logical zero (block 38). Next, the bridge 26A-Dchecks the page roll attribute setting (block 40). If the page rollattribute is set to a logical zero, then normal PCI-X logic functions byretrieving the data and storing it in the buffer so that it may bedelivered to the requester (block 42). If the page roll attribute is setto a logical one, then the data requested is retrieved up to the 4 KBboundary and stored in the buffer (block 44). After that portion of thedata has been read and returned to the requester, a page roll occurs(block 46). Finally, the data above the 4 KB boundary is read into thebuffer, and delivered to the requester to complete the transaction(block 48).

The determination of whether a memory read block transaction crosses amemory boundary (Block 34 of FIG. 2) may be represented by a logicflowchart as illustrated in FIG. 3. Two scenarios may be checked tocompute whether the transaction crosses the memory boundary. In thefirst scenario, if the PCI-X starting address (block 52) is not alignedto the 4 KB boundary and the PCI-X byte (block 54) count is 4 KB (block56), then the transaction crosses a 4 KB memory boundary (block 58).Thus, the page roll attribute is set to a logical one. However, if theaddress is aligned to the 4 KB boundary and the byte count is 4 KB, thenthe transaction does not cross the memory boundary. The bridge 26A-Ddetermines whether the transaction crosses the memory boundary by addingthe starting address and the byte count of the transaction (block 60).Thus, the page roll attribute is set to a logical zero so that thebridge 26A-D reads and delivers the data from the starting address tothe memory boundary (block 38).

The second scenario takes place when the PCI-X starting address (block52) and the PCI-X byte count (block 54) are added (block 60) todetermine whether a transaction crosses the memory boundary. Block 62illustrates the algorithm. If bit 12 has a logical value of one and atleast one bit from 11 through 0 is a logical one, then the transactioncrosses the 4 KB memory boundary (block 64). However, if the abovecondition is not true, then the transaction does not cross the memoryboundary (block 66). If the transaction does not cross the memoryboundary, then a page roll is not utilized. Accordingly, the data isread and delivered to the requester without initiating a page roll.

FIG. 4 illustrates a flow chart depicting a buffer page rollimplementation method for PCI-X read block transactions. Moreparticularly, FIG. 4 illustrates the actions taken for the generation ofa page roll. After the bridge 26A-D checks whether a page roll isrequired (block 40) and determines that a page roll is necessary, alldata up to the boundary level is delivered to the requester (block 44).However, if a page roll is not required, then normal logic controls(block 42). After the data within the boundary address is delivered tothe requester a page roll occurs. The starting address of the buffer isgiven a new address within the memory 22. This new address is theboundary address (block 76). The number of cachelines required is set tothe number of cachelines needed after the 4 KB memory boundary (block72).

The bridge 26A-D logic computes the memory boundary address by takingthe buffer base address bits and adding one (block 74). This computationmay take up to two clock cycles. Subsequently, the buffer base addressmay be replaced with the memory boundary address (block 76). Once allthe data up to the memory boundary has been delivered to the requester,the required buffer data may be replaced with the required amount ofcachelines after the memory boundary page (block 72). The total numberof cachelines needed to satisfy a PCI-X transaction is discussed below.

As mentioned above, memory 22 is generally divided into groups of bytescalled cachelines. Within the memory 22 a certain number of cachelinesare located within the memory boundary. Therefore, for a page roll totake place, the number of cachelines requested by an operator isdetermined to exceed the memory boundary. For example, a 4 KB boundarymaintains a certain number of cachelines, and when the requested amountexceeds the boundary, a page roll is initiated. The algorithm forcomputing the number of cachelines used to implement a page roll isshown in FIG. 5.

FIG. 5 illustrates a flow chart for computing the total number ofcachelines used to implement a page roll for a PCI-X read transaction.It should be noted again that determining whether a transaction crossesa memory boundary utilizes the PCI-X starting address (block 81) and thePCI-X byte count (block 82). If the PCI-X byte count (block 82) is 4 KB(block 84) and the PCI-X starting address (block 81) aligns to acacheline (block 86), then the total cachelines used equals 80h (block88). However, if the address is not aligned to the cacheline, then thetotal cachelines used equals 81 h (block 90).

If the starting address (block 81) is aligned to the cacheline (block94), then bridge 26 A-D determines whether the byte count (block 82) isaligned to the cacheline (block 96). Thus, if the byte count aligns tothe cacheline, then the total cachelines equal the PCI-X byte count(block 98). However, if the byte count does not align to the cacheline,then the total cachelines equal the byte count plus one (block 100) notequal to the memory boundary, then the bridge 26A-D continues to checkwhether the byte count is aligned to the cacheline (block 102). The samefunction occurs if the address is aligned to the cacheline (block 96).

If starting address is not aligned to the cacheline (block 94) then thebridge 26A-D determines whether the byte count is aligned to thecacheline (block 102). If the byte count does align to the cacheline,then the total cacheline equal the byte count plus one (block 104).However, if the byte count is not aligned to a cacheline (block 102),then the bridge 26A-D determines whether the sum of the starting addressand the byte count crosses the cacheline (block 106). Therefore, if thesum of the starting address and byte count cross the cacheline, thetotal cachelines equal the byte count plus two (block 108). However, ifthe sum of the starting address and the byte count do not cross thecacheline, then the total cachelines equal the byte count plus one(block 110). Although the above embodiment uses a 4 KB boundary, otherlevels may be used, and the example set above is not limited by anyparticular memory boundary limit, for example memory boundary levels mayinclude 4 KB, 8 KB, and 16 KB.

FIG. 6 illustrates a flow chart demonstrating an exemplary algorithm forcalculating the number of cachelines before the memory boundary. In thisexample a 4 KB boundary is used, however different boundary levels, forexample 8 KB, 16 KB, 32 KB, etc. may be used. The bridge 26A-Ddetermines whether the transaction crosses the memory boundary (block122) and determines the number of cachelines needed before and after thememory boundary using the PCI-X starting address (block 124) and thePCI-X byte count (block 126). If the transaction crosses the 4 KBboundary (block 122), and if the PCI-X byte count (block 126) is equalto the 4 KB (block 128), then the cachelines before the 4 KB boundaryequals 80 h (block 130). Although if the byte count is not 4 KB, (block128) then the cachelines before the 4 KB page equals a twos complementof the address plus one (block 132).

On the other hand, if the transaction never crosses the 4 KB boundary(block 122), then the system 10 checks whether the address aligns with acacheline (block 134). Furthermore, if the address is aligned to thecacheline, then the byte count is checked to determine whether it alignsto a cacheline (block 136). If the byte count is aligned to thecacheline, then the cachelines before the 4 KB boundary page equals thebyte count (block 138). The cachelines before the 4 KB boundary pageequals the byte count plus one (block 140), if the byte count is notaligned to the cacheline (136).

If the transaction does not cross the 4 KB boundary (block 122), and theaddress is not aligned to the cacheline (block 134), then the bridge26A-D checks whether the byte count is aligned to the cacheline (block142). If the byte count is aligned, then the cachelines before the 4 KBboundary page equals the byte count plus one (block 144). Now, if thebyte count does not align to the cacheline, then the starting addressand the byte count are added together (block 146). If the startingaddress and the byte count crosses the cacheline, then the cachelinesbefore the 4 KB boundary equal the byte count plus two (block 148).However, if it does not cross the cacheline, then the cachelines beforethe 4 KB boundary equal the byte count plus one (block 150). Asmentioned above, it should be understood that the technique is notlimited to the 4 KB boundary and is merely being provided by way ofexample. For instance, a 8 KB boundary, 16 KB boundary or any other suchvalue may be used to accomplish these goals.

In an alternative embodiment of the present invention, a page roll isnot used. Instead of a page roll, a transaction may be allocated twobuffers if the transaction is a memory read block transaction andcrosses a memory boundary. A single read block transaction occupies twobuffers inside the bridge 26A-D, and the data for the entire transactionis returned in address order. Allocating two buffers also may requireadditional synchronization logic to ensure that data is returned in theorder required by the PCI-X specification. As with the previousembodiment, the advantage of this alternative embodiment is that all thedata is read and delivered to the requester. Whereas, prior to thepresent techniques only the data read to the boundary could be returnedto the requester. However, the disadvantage to this embodiment ascompared to the previous embodiment is that it uses additional spacewithin the bridge 26A-D. Because space within the bridge 26A-D islimited, additional transactions may not be serviced until thetransaction using two buffers has been processed.

FIG. 7 illustrates a flow chart demonstrating a dual buffer method forallocating PCI-X transactions that cross address boundaries within abuffer queue. When a new PCI-X transaction is detected (block 162), thebridge 26A-D determines whether the transaction is a memory read blocktransaction that crosses a 4 KB memory boundary (block 164). FIG. 3illustrates the steps taken by the bridge 26A-D to determine whether thetransaction is a memory read block transaction that crosses the memoryboundary. Although a page roll is not utilized, this technique alsoincorporates the algorithm in FIG. 5 and FIG. 6 to determine whether asecond buffer is required.

If the bridge 26A-D determines that the transaction is a memory readblock transaction that crosses the 4 KB memory boundary, then twobuffers are allocated for the transaction (block 166). However, if thebridge 26A-D determines that the transaction is not a memory read blocktransaction or does not cross the 4 KB boundary, then the transaction isallocated only one buffer (block 168). Thus, the data stored within thesingle buffer is read and delivered to the requester according to normaloperation. It should be noted that logical devices within bridge 26A-Ddetermine whether two buffers need to be allocated for the read blocktransaction. Determination is made as to whether the transaction crossesthe memory boundary according to FIG. 3. Additionally, FIG. 5. and FIG.6 illustrate the specific calculations utilized by the logic devices todetermine if the transaction crosses the memory boundary. Thus, once thedetermination is made, for instance, if the memory boundary is crossed,then an additional buffer is allocated. However, if the memory boundaryis not crossed by the read block transaction, then an additional bufferis not allocated.

FIG. 8 illustrates a flow chart depicting logic to ensure the secondbuffer delivers data after the first buffer has completed delivering therequested data. At the time of allocation, if the transaction uses anallocation of two buffers (block 172), then the buffer number of thefirst buffer in the allocation is saved, and a mark is set indicatingthe second buffer to wait for the first buffer to finish (block 174).However, if one buffer is sufficient for the read block transaction,then the mark is cleared so that the buffer will return the data withoutwaiting for another buffer to finish (block 176).

FIG. 9 illustrates a flow chart of logic to ensure that a secondarybuffer reads and delivers data after a first buffer has completed alldata delivery requirements. If the read block transaction uses twobuffers (block 172), and then the saved buffer number is used by thebridge 26A-D to determine whether the first buffer has finishedreturning the data (block 182). For instance, once the data is read fromthe starting address to the memory boundary, all data is returned to thePCI-X device, thus indicating to the bridge 26A-D that the first bufferhas finished returning the data. Therefore, the bridge 26A-D waits untila signal is received, indicating that the first buffer has finishedreturning the data (block 184). If there is no indication that thebuffer has finished returning the data, then the logic device waitsuntil an indication is given that the buffer has finished reading thedata (block 186). However, if the allocation does not require twobuffers (block 172), then the data is returned as soon as a legal PCI-Xtransaction can be initiated.

While the invention may be susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, it should be understood that the invention is not intended tobe limited to the particular forms disclosed. Rather, the invention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

1. A method for processing a read block transaction requested from aPCI-X device, the method comprising the acts of: a) determining whethera read block transaction having a starting address and a ending addresscrosses a memory boundary; b) if the read block transaction crosses thememory boundary, reading data from the starting address to the memoryboundary into a first buffer; and c) reading data from the memoryboundary to the ending address of the read block transaction into asecond buffer.
 2. The method as in claim 1, wherein act (a) comprisesthe acts of: determining whether the starting address is aligned withthe memory boundary; determining whether a sum of the starting addressand byte count of the read block transaction exceeds the memoryboundary; and if the starting address is not aligned with the memoryboundary and if the sum of the starting address and byte count is equalto the memory boundary, providing an indication that the read blocktransaction crosses the memory boundary.
 3. The method as in claim 2,wherein the act of providing an indication comprises the act of settinga page roll attribute to a logical
 1. 4. The method as in claim 1,wherein if the read block transaction does not cross the memoryboundary, reading data from the starting address to the ending addressinto the first buffer.
 5. The method as in claim 1, wherein act (a)comprises the act of computing whether the read block transactioncrosses the memory boundary by adding the starting address of the readblock transaction and the byte count of the read block transaction. 6.(Cancelled).
 7. (Cancelled).
 8. The method as in claim 1, comprising theact of delivering data from each of the first and second buffers to thePCI-X device.
 9. The method as in claim 1, wherein the memory boundaryis equal to 4 KB.
 10. The method as in claim 1, wherein a byte count forthe read block transaction is 4 KB.
 11. The method as in claim 1,wherein acts (a) through (c) are performed in the recited order.
 12. Asystem for processing a read block transaction requested from a PCI-Xdevice, comprising: means for determining whether a read blocktransaction having a starting address and an ending address crosses amemory boundary; means for reading data from the starting address up tothe memory boundary into a first buffer, if the read block transactioncrosses the memory boundary; and means for reading data from the memoryboundary to the ending address of the read block transaction into asecond buffer.
 13. The system of claim 12, wherein the determining meanscomprises: means for determining whether the starting address is alignedwith the memory boundary; means for determining whether a sum of thestarting address and byte count of the read block transaction exceedsthe memory boundary; and means for providing an indication that the readblock transaction crosses the memory boundary, if the starting addressis not aligned with the memory boundary.
 14. The system of claim 13,wherein the means for providing an indication that the read blocktransaction crosses the memory boundary comprises means for setting apage roll.
 15. The system of claim 12, comprising means for reading datafrom a starting address to the ending address into the first buffer, ifthe read block transaction does not cross the memory boundary.
 16. Thesystem of claim 12, comprising means for calculating whether the readblock transaction crosses the memory boundary by adding the startingaddress and read block transaction byte count.
 17. (Cancelled). 18.(Cancelled).
 19. The system of claim 12, further comprising means fordelivering data from each of the first and second buffers to the PCI-Xdevice.
 20. The system of claim 12, further comprising means fordetermining whether a read block transaction having a starting addressand a ending address crosses a 4 KB memory boundary.
 21. A tangiblemedium for processing a read block transaction requested from a PCI-Xdevice, the tangible medium comprising: a) a routine for determiningwhether a read block transaction having a starting and an ending addresscrosses a memory boundary; b) a routine for reading data from thestarting address up to the memory boundary into a first buffer, if theread block transaction crosses the memory boundary; and c) a routine forreading data from the memory boundary to the ending address of the readblock transaction into a second buffer.
 22. The tangible medium as inclaim 21, wherein routine (a) comprises: a routine for determiningwhether the starting address is aligned with the memory boundary; aroutine for determining whether a sum of the starting address and bytecount of the read block transaction exceeds the memory boundary; and aroutine for providing an indication that the read block transactioncrosses the memory boundary, if the starting address is not aligned tothe memory boundary.
 23. The tangible medium as recited in claim 22,wherein the routine for providing an indication comprises: a routine forproviding an indication that the read block transaction crosses thememory boundary; and a routine for setting a page roll attribute to alogical
 1. 24. The tangible medium as in claim 22, wherein the routinefor determining whether the sum of the starting position address andbyte count of the read block transaction comprises a routine forcalculating whether the read block transaction crosses the memoryboundary by adding the starting address and the byte count of the readblock transaction.
 25. (Cancelled).
 26. The tangible medium as in claim21, comprising a routine for delivering data from each of the first andsecond buffers to the PCI-X device.
 27. The tangible medium as in claim21, comprising a routine for reading data from the starting address upto a 4 KB memory boundary into the first buffer.
 28. The tangible mediumas in claim 21, wherein the tangible medium comprises at least one of aread only memory, a random access memory, a disc, an applicationspecific integrated circuit, and a programmable logic device.
 29. Asystem for processing a read block transaction requested from a PCI-Xdevice comprising: at least one processor; a memory operatively coupledto the at least one processor; and at least one bridge operativelycoupled to the memory and configured to receive a read blocktransaction, the bridge configured to determine whether a read blocktransaction having a starting address and an ending address transactioncrosses a memory boundary, wherein if the block transaction crosses thememory boundary read data from the starting address to the memoryboundary into a first buffer, and read data from the memory boundary tothe ending address of the read block transaction into a second buffer.30. The system of claim 29, wherein the bridge determines whether thestarting address is aligned to the memory boundary.
 31. The system ofclaim 29, wherein the bridge provides an indication that the read blocktransaction crosses the memory boundary, if the starting address is notaligned to the memory boundary.
 32. (Cancelled).
 33. The system of claim29, wherein data from the starting address to the ending address is readinto the first buffer, if the read block transaction does not cross thememory boundary.
 34. The system of claim 29, wherein the bridge computeswhether the memory boundary is crossed by the read block transaction byadding the starting address and byte count of the read blocktransaction.
 35. (Cancelled).
 36. The system of claim 29, wherein thebridge delivers data from each of the first and second buffers to thePCI-X device.
 37. The system of claim 29, wherein the memory boundary isequal to 4 KB.
 38. A method for processing a read block transactionrequested from a PCI-X device, the method comprising the acts of: a)determining whether a read block transaction having a starting addressand an ending address crosses a memory boundary; b) if the read blocktransaction crosses the memory boundary, allocating a plurality ofbuffers for the read block transaction, reading data from the startingaddress up to the memory boundary into a first buffer of the pluralityof buffers; and c) reading data from the memory boundary to the endingaddress of the read block transaction into a second buffer of theplurality of buffers.
 39. The method as in claim 38, wherein act (a)comprises the acts of: determining whether the starting address isaligned with the memory boundary; determining whether the sum of thestarting address and byte count of the read block transaction exceed thememory boundary; and if the starting address is not aligned to thememory boundary and if the sum of the starting address and byte count isequal to the memory boundary, providing an indication that the readblock transaction crosses the memory boundary.
 40. The method as inclaim 39, wherein the act of providing an indication comprises the actof allocating the plurality of buffers to the read block transaction.41. The method as in claim 38, wherein if the read block transactiondoes not cross the memory boundary, reading data from the startingaddress to the ending address into the first buffer.
 42. The method asin claim 38, wherein act (a) comprises the act of computing whether theread block transaction crosses the memory boundary by adding thestarting address and read block transaction byte count.
 43. (Cancelled)44. The method as in claim 38, comprising the act of delivering datafrom the first and second buffers to the PCI-X device.
 45. The method asin claim 38, wherein the memory boundary equals 4 KB.
 46. The method asin claim 38, wherein acts (a) through (c) are performed in the recitedorder.